Workshop-Programm zur SCD 2008  
   
Download Programm/Messeflyer als Pdf
   
A1 Wednesday, April 23, 2008

 

   
Get together and Welcome
A. zu Hohenlohe, R. Weigel, M. Schroeter, F. Ellinger
8:40am - 9:00 am
   
Semiconductor Technologies  
   
The Limits of Microelectronics - a never ending
story, INVITED

J. W. Bartha, TU Dresden
9:10 am - 9:50 am
   

Transistor Design and Optimization for achieving
Record RF Performance in Silicon Technologies, INVITED

B. Jagannathan, IBM, USA

10:10 am - 10:50 am
   
SiGe HBT BiCMOS Technologies for High-Speed
Applications, INVITED

B. Heinemann, IHP GmbH, Frankfurt/Oder
11:10 am - 11:50 am
   
High-Voltage High-Frequency (L)DMOS Technology, INVITED
HV. Dudek, Atmel
12:10 pm - 12:50 pm
   
Radio Frequency Integrated Circuits and Systems I  
   
Highly Flexible Transmitter Architectures in
Nano-Scale CMOS, INVITED

C. Wicpalek, G. Hueber, G. Strasser,
B. Neurauter, DICE Linz
1:50 pm - 2:30 pm
   
Integrated Power Amplifiers, INVITED
G. Böck, TU Berlin, Microwave Engineering Lab.
2:40 pm - 3:20 pm
   
Technology Status and Perspectives for Multi-band
and Multistandard Challenges in Upcoming
RF-Frontends, INVITED

T. Richter, P. Zampardi,
Skyworks Solutions, Inc.
3:40 pm - 4:20 pm
   
Integrated RF-Circuit Design for OFDM MIMO
Systems, INVITED

M. Simon, Infineon Technologies,
R. Weigel, Universität Erlangen-Nürnberg
4:40 pm - 5:20 pm
   
Low Cost RF Adaptive Antenna Combining
R. Eickhoff, F. Ellinger, U. Mayer,
Dresden University of Technology, Chair for
Circuit Design and Network Theory,
I. Santamaría, University of Cantabria
5:40 pm - 6:00 pm
   
A2 Wednesday, April 23, 2008  
Integrated Circuits and Devices for Optical Communication  
   
Dense Optical Integrated Circuits at Tb/s Data Rates -
Concepts and Technological Challenges, INVITED

H. Jäckel, ETH Zurich, Electronics Lab, Ife
9:10 am - 9:50 am
   

Efficient design of high-speed ICs beyond 100 Gb/s
with special regard to SiGe-bipolar technology

M. Möller, Saarland University, and Micram
Microelectronic GmbH

10:10 am - 10:50 am
   
A Power- and Area- Optimized 10 Gb/s VCSEL Driver for
very High Density Data-Link Applications in 90-nm CMOS

J. Weiss, T. Morf, M. L. Schmatz
IBM Zurich Research Laboratory
P. Emma, IBM T.J. Watson Research Center
H. Jaeckel, ETH Zurich, Electronics Lab, Ife
11:10 am - 11:30 am
   
A 4.5-5.3 GHz Quadrature VCO with Complementary
Couplers in 0.25 µm CMOS

G. von Büren, L. Rodoni, D. Barras, S. Wehrli,
H. Jäckel ETH Zurich, Electronics Lab.,
F. Ellinger, Dresden University of Technology
11:50 am - 12:10 pm
   
Compact and Low Power CMOS Decision Circuit up to
20 Gb/s in 90 nm CMOS

L. Rodoni, G. von Büren, H. Jäckel,
ETH Zurich, Electronics Lab.,
F. Ellinger, Dresden University of Technology
A. Huber, Fachhochschule Nordschweiz, IME
12:30 am - 12:50 pm
   
Modeling of Integrated Devices  
   
Noise in Advanced Transistors, INVITED
M. Berroth, Universität Stuttgart
1:50 pm - 2:30 pm
   
Compact Modeling for HF Circuit Design, INVITED
M. Schroeter, TU Dresden,
Electron Devices and Integrated Circuits
2:50 pm - 3:30 pm
   
III-V HBTs - Technology, Modeling and Applications, INVITED
M. Rudolph, Ferdinand-Braun-Institut für
Höchstfrequenztechnik
3:50 pm - 4:30 pm
   
Photodiode Modeling for Optoelectronic Integrated Circuits
J. Sturm, Carinthia University of Applied
Sciences, H. Zimmermann, TU Wien, Institut
für Elektrische Mess-und Schaltungstechnik
4:50 pm - 5:10 pm
   
   
A3 Wednesday, April 23, 2008  
   
Industrial Session  
   
Software-Defined Test Systems for Verification
and Validation of Integrated Circuits

C. Gindorf, National Instruments Germany
9:10 am - 10:10 am
   
Extending Power Device Testing to the Wafer Level:
New Test Capability for Power Devices

R. Zowada, Cascade Microtech Germany
10:30 - 11:15
   
A Methodology for High Speed Channel Design
and Optimization

D. Crawford, Ansoft
11:30 am - 12:00 pm
   
Using Wafer-Level Device Characterization and
Reliability Test to streamline the Development Cycle

B. Hirschfeld, SUSS MicroTec
12:10 pm - 1:00 pm
   
Correct Power Dissipation through digital Power
Factor Correction (PFC)

S. Brenner, Productivity Engineering
Gesellschaft für IC Design mbH
2:00 pm - 2:25 pm
   
R+D subsidies - periods of commitment, reclaim, liability
F+E Förderung - Bindungsfristen, Rückforderung, Haftung

D. Kresser, Kanzlei Nörr Stiefenhofer
Lutz & Partnerschaft
3:20 pm - 4:20 pm
   
Factory Tour in the Clean Rooms at RHe
Microsystems GmbH
Participation free of any costs. For 6-8 Persons only.
Advanced Registration necessarily required.
In case of interest tour can be additionally arranged
on Thursday.
From the Semiconductor/Bare Dies to the functionally
tested electronics module.
Board Manufacturing - Die Attach - Chip Packaging - Wire
Bonding - Multi-Chip-Modules and Customized System in
Packages - Test Boards - Automatic Assembly
Deperture from
Kulturpalast

1:15 pm

Arrival

3:10 pm
   
Come together Sven Helbig Jazz Trio

We are looking forward to present one of the outstanding
jazz formations within Saxony- the Sven Helbig
Trio (piano, bass and drums).
Be inspired by their fresh and virtuosic interpretations
of classical and modern jazz music.
Well known by their cooperation with bands such as the
Pet-Shop Boys, Rammstein and by the foundation
of the Dresdner Sinfoniker, the Sven Helbig Trio will be
the cultural highlight of the evening!
6:00 pm

jazz
   
B1 Thursday, April 24, 2008
   
Silicon Saxony - My Favorite Place
D. Landgraf-Dietz, SILICON SAXONY
8:40 am - 9:00 am
   
Packaging  
   
System Integration - Recent Developments in
Electronic Packaging, INVITED

T. Zerna, TU Dresden,
Center of Microtechnical Manufacturing,
K.-J. Wolter, TU Dresden,
Electronic Packaging Laboratory
9:10 am - 9:50 am
   
DIONYSYS - Design Technology for Radio Frequency
Systems in Package

U. Knöchel, Fraunhofer IIS/EAS Dresden
H.-J. Golberg, Atmel Germany GmbH Ulm

10:00 am - 10:20 am
   
Through Silicon Contacts for IC and Sensoric Application
K. Viehweger, K. Richter, U. Künzelmann, H.
Wojcik, U. Merkel, A. Hiess, A. Jahn,
C. Wenzel, J.W. Bartha, TU Dresden,
Institut für Halbleiter- und Mikrosystemtechnik
10:40 am - 11:00 am
 
Preparation and Investigation of Thin Coated Au and
Cu Wires for US Wedge Wedge Bonding at
Room Temperature
C. Nobis, C. Klaus, H. Hiemann, F. Rudolf, C.
Wenzel, J.-W. Bartha, TU Dresden,
Institut für Halbleiter- und Mikrosystemtechnik
11:10 am - 11:30 am
 
Wafer Level Package Technology for DRAM -
Current Status and Future Challenges

S. Dobritz, Qimonda AG
11:40 am - 12:00 pm
 
E´less Nickel/Palladium/Gold as Universal Surface
Finish for Soldering/Bonding Application in
Semiconductor Industry

A. Uhlig, Atotech Deutschland GmbH
12:10 pm - 12:30 pm
 
Short Introduction and Overview for Sensors which
are needed in a High Temperatur plus
Frequency Independent Package

H. Fischer, H+B Ingenieurbüro und
Unternehmensberatung GmbH
12:40 pm - 1:00 pm
 
Radio Frequency Integrated Circuits and Systems II  
 
Multifunctional Si/SiGe ICs for low-power microwave
and millimeter- wave applications, INVITED

H. Schumacher, Universität Ulm
2:00 pm - 2:40 pm
 
SiGe Frontends with Data Rates of Several Gb/s for
Short-Range Wireless Communication at 60 GHz and
Beyond, INVITED

C. Scheytt, IHP GmbH, Frankfurt/Oder
2:50 pm - 3:30 pm
 
High-speed mmWave and THz circuits in silicon
process technologies, INVITED

U. Pfeiffer, Universität Wuppertal
3:40 pm - 4:20 pm
 
High Frequency Circuit Design in SOI CMOS, INVITED
F. Ellinger, Chair for Circuit Design and
Network Theory, TU Dresden
4:30 pm - 5:10 pm
 
Test of Differential 2.4 GHz IEEE 802.15.4/ZigBee
™ICs: Limits and Challenges

B. Bieske, Institut für Mikroelektronik- und
Mechatronik-Systeme gGmbH, Ilmenau
M. Lange, S. Beyer, Atmel, Heilbronn
5:20 pm - 5:40 pm
 
B2 Thursday, April 24, 2008

 

   
Future Trends in Test Technologies, INVITED
K. Luther, Infineon Technologies, Neubiberg
9:10 am - 9:50 am
   

Residual Stress Measurement on Semiconductor
Layers Utilizing Stress Relief Techniques

F. Luczak, B. Michel, A. Gollhardt, D. Vogel,
Fraunhofer IZM, Micro Materials Center
Chemnitz,
U. Lehr, M. Grillberger, V. Jaschke,
H. Geisler, AMD Saxony, Dresden

10:00 am - 10:20 am
   
Low Implantation Dose Measurement with a Surface
Charge Profiling Method (QCS Tool)

M. Sukowski, F. Heider, Infineon Technologies,
Villach (A), G.Krzych, QC Solutions, Inc., Alzenau
10:30 am - 10:50 am
   
Die Level Screening Methods for Statistical
Post-Processing at Wafer Test

A. Kaestner, F. Ruckerbauer,
Infineon Technologies Regensburg
11:00 am - 11:20 am
   
CMP for the Fabrication of Advanced MEMS Devices
G. Zwicker, Fraunhofer Institut fuer
Siliziumtechnologie ISIT
11:40 am - 12:00 pm
   
Design and Implementation of an Automated
Test Environment for Signal-Acquisition ASICs

Ch. Jakobi, F. Wagner, J.M. Tomasik, K. M.
Hafkemeyer, W. Galjan, D. Schroeder, W. H.
Krautschneider, TU Hamburg-Harburg
12:20 pm - 12:40 pm
   
Plenary Talk  
   
President of Business Group Communication
Solutions Member of the Executive Management
Board Infineon Technologies

Moore's Law and RF Design - Conjoint or Diverging ?
1:30 pm - 2:30 pm
   
Fabrication and Testing II  
   
3D Imager Bare Die Qualification according to
AEC-Q100-Rev-F

L. Lehmann, IEE Vision Sensing GmbH
2:40 pm - 3:00 pm
   
Improved Prime Wafer Geometry by Advanced
Capabilities of Polishing Processes

G.Moersch, J. Kanzow, M. Langenkamp, S.
Werth, M. Lauter, Peter Wolters GmbH
3:10 pm - 3:30 pm
   
Design And Fabrication Of An Embedded
SONOS-Memory-Module For CMOS-Technologies

M. Wickert, F. Ellinger, R. Schüffny, TU
Dresden, R. Herberholz, F. Roger, P. Wensley,
A. Cuthbertson, ATMEL North-Tyneside,
F. Roger als Co-Author
3:40 pm - 4:00 pm
   
B3 Thursday, April 24, 2008  
   
RFIC lecture session at TUD: Reflection Coefficient,
Smith Chart, S-Parameter and Impedance Transformation

F. Ellinger, Dresden University of
Technology,Chair for Circuit Design and
Network Theory
9:20 am - 10:50 am
   
Digital Circuit Design  
   
Bio-Inspired IC System Design -
What can Chip Designers learn from Nature? INVITED

A. Herkersdorf, TU München
11:10 am - 11:50 am
   
Qualification of Mixed-Signal Components by Way
of an Automotive Control Unit
C. Heinz, H. Rauch, iSyst GmbH
12:00 pm - 12:20 pm
   
Gate-Level Digital Power Simulation with Varying
Technology Parameters
U. Eichler, J. Haase,
Fraunhofer IIS/EAS Dresden,
R. Häußler, H. Kinzelbach,
Infineon Technologies, Munich
12:40 pm - 1:00 pm
   
Sensor Circuits and Systems  
   
A CMOS Receiver Prototype for 5.8 GHz Wireless
Local Positioning System

M. Krcmar, V. Subramanian, G. Böck,
TU Berlin, Microwave Engineering Lab
2:00 pm - 2:20 pm
   
A 900 MHz / 2.45 GHz RF Front-End for Passive
RFID Transponders

Q. Fu, N. Gay, C. Bansleben, R. Hildebrand, W.
J. Fischer, Fraunhofer Institut für Photonische
Mikrosysteme (IPMS)
2:30 pm - 2:50 pm
   
A Dynamically Configurable very Low-Power
Sensor Interface for Microwave RFID Transponders

N. Gay, Q. Fu, C. Bansleben, R. Hildebrand,
W.-J. Fischer
3:00 pm - 3:20 pm
   
Linear Frequency Ramp Generation for Local Positioning
R. Eickhoff, F. Ellinger, Dresden University of Technology,
T. Ußmüller, University of Erlangen-Nuremberg,
J. Hüttner, R. Gierlich,
Siemens AG Munich
3:30 pm - 3:50 pm
   
REACH Requirement - Legal Consequences for
the Semiconductor Industries

M. A. Ahlhaus, Kanzlei Nörr Stiefenhofer Lutz & Partnerschaft
4:00 pm - 4:20 pm
   
BOOTH PRESENTATIONS  
   
April 23, 2008
RFIC Inductor & Interconnect Modelling

Dr. Mühlhaus Consulting & Software GmbH
10:50 am - 11:10 am
   
April 24, 2008
SUSS MicroTec

Wafer-level RF & Microwave Testing
9:50 am - 10:10 am
   
April 24, 2008
Robotron Datenbank-Software GmbH

Effective Analysis of Wafer Defects at AMD 36 LLC using
a Modern Error Tracking System
11:20 am - 11:40 am
   
Goodbye 5:40 pm - 5:50 pm